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[Windows Develop] fir

Description: fir 滤波器 Systems generator 实现并转化为verilog语言-fir Filter Systems generator to achieve and into verilog language
Platform: | Size: 2671616 | Author: lynn | Hits:

[Books] fir

Description: 本文以软件无线电为指导，提出基于CORDIC算法利用FPGA平台数字下变频器设计方案。首先分析下变频器的结构；然后采用模块化设计思想，将数字下变 频的功能模块包括数字控制振荡器、CIC抽取滤波、HBF抽取滤波器、FIR低通滤波器进行分析和FPGA的设计；最后在 MATLAB/DSPBuilder下硬件仿真模块进行仿真并给出仿真结果。-In this paper, software-defined radio as the guidance, based on the CORDIC algorithm uses the FPGA platform, digital down-converter design. First analyzes the structure of down-converter and then use a modular design concept, the digital down-conversion function modules including digital controlled oscillator, CIC decimation filtering, HBF decimation filter, FIR low-pass filter for analysis and FPGA design the final In the MATLAB/DSPBuilder under the hardware emulation module simulation and simulation results.
Platform: | Size: 201728 | Author: jiang | Hits:

[VHDL-FPGA-Verilog] 11FIRfliter

Description: 11阶FIR滤波器和（7，4）编码器的Verilog语言，高手的作品，放心下-11-order FIR filter, and (7,4) encoder of the Verilog language, master' s works, rest assured that the next
Platform: | Size: 2048 | Author: 王刚 | Hits:

[VHDL-FPGA-Verilog] cic_intp_64_four

Description: 4阶CIC内插滤波器，内插系数64，Verilog版本，数字下变频-4-order interpolating CIC filter interpolation factor of 64, Verilog version of the digital down-conversion
Platform: | Size: 1024 | Author: 王刚 | Hits:

[VHDL-FPGA-Verilog] fir_dec3

Description: FIR抽取滤波器，抽取系数3，Verilog版本，数字下变频-FIR decimation filter, extraction coefficient of 3, Verilog version of the digital down-conversion
Platform: | Size: 2048 | Author: 王刚 | Hits:

[Program doc] 103244864FIR_filter_DA_machine

Description: 简易fir滤波器，采用分布式算法实现，verilog-Simple fir filter using distributed algorithm, verilog
Platform: | Size: 1024 | Author: wang | Hits:

[VHDL-FPGA-Verilog] fir_16

Description: 用Verilog写的fir滤波器，16阶8位位宽，看看吧-Written using Verilog fir filter, 16-order 8-bit wide, to see if it
Platform: | Size: 743424 | Author: 刘安 | Hits:

[VHDL-FPGA-Verilog] FIR_chanbing

Description: FIR滤波器的verilog HDL语言编写的，希望对大家有用-FIR filter verilog HDL languages, we hope to be useful
Platform: | Size: 13312 | Author: | Hits:

[VHDL-FPGA-Verilog] fir

Description: FIR滤波器，使用Verilog硬件描述语言进行编程-FIR filter, using the Verilog hardware description language programming
Platform: | Size: 1024 | Author: zhaoyf | Hits:

[VHDL-FPGA-Verilog] FIR_Filter

Description: verilog的32阶FIR低通滤波器描述-verilog 32-order FIR low-pass filter described
Platform: | Size: 1378304 | Author: yuanjun | Hits:

[VHDL-FPGA-Verilog] fir-filter

Description: fft的vhdl实现源代码，具体的有心情有兴趣的可以自己下载下来看下，因为我也是在入门中不懂。-fft verilog HDL
Platform: | Size: 7241728 | Author: liu | Hits:

[VHDL-FPGA-Verilog] fir-filter

Description: 11阶fir数字滤波器的verilog程序设计，线性相位，系数量化处理-11 order of fir digital filter verilog programming, linear phase, the coefficient quantization
Platform: | Size: 59392 | Author: happy | Hits:

[VHDL-FPGA-Verilog] FIR

Description: 10阶的F.I.R滤波器设计的 verilog代码-Verilog code for the 10-order FIR filter design
Platform: | Size: 1024 | Author: lubianke | Hits:

[Editor] FIR-verilog

Description: FIR filter verilog code
Platform: | Size: 711680 | Author: jeren1228 | Hits:

[Industry research] 8-channel-FIR

Description: b channel FIR filter verilog
Platform: | Size: 113664 | Author: jeren1228 | Hits:

[VHDL-FPGA-Verilog] fpga-fir

Description: xlinx fpga 利用verilog语言实现fir滤波器功能，完整ise工程文件直接可以使用-xlinx fpga verilog language the fir filter function, complete ise project file can be used directly
Platform: | Size: 1006592 | Author: bambod | Hits:

[VHDL-FPGA-Verilog] fir

Description: 16阶的FIR滤波器的verilog文件，包含了测试报告。-16 order FIR filter verilog file contains a test report.
Platform: | Size: 41984 | Author: luna | Hits:

[Other] filter

Description: verilog implementation of structural FIR filter. Contains testbench, including sample data and coefficients.
Platform: | Size: 2211840 | Author: kimchiman | Hits:

[VHDL-FPGA-Verilog] fir

Description: 利用VHDL和Verilog HDL语言实现FIR滤波器-Using VHDL and Verilog HDL language to realize FIR filter
Platform: | Size: 49152 | Author: 姚远 | Hits:

[Software Engineering] verilog

Description: 最长的那个句子，求sum的赋值语句就是FIR滤波器的计算过程，将二进制乘法转化为移位运算。对于小数点后的乘数是向左移，小数点前的乘数是往右移位。 -The longest sentence, find the sum of the assignment statement is the calculation of the FIR filter, the binary multiplication into shift operation. Multiplier after the decimal point to the left, in front of the decimal point multiplier is shifted to the right.
Platform: | Size: 1024 | Author: jee | Hits:
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